Micron’s new uMCP5 packaging builds on the company’s innovation and leadership in multichip form factors. Micron uMCPs combine low-power DRAM with NAND and an onboard controller, using 40% less space compared to a two-chip solution. This optimized configuration saves power, reduces memory footprint and enables smaller and more agile smartphone designs.
“Featuring the latest LPDRAM and UFS interface, this first-in-the-industry packaging solution offers a 50% increase in memory and storage bandwidth while reducing power,” said Dr. Raj Talluri senior vice president and general manager at Micron. “Our new uMCP5 package enables midrange 5G smartphones to operate with the ultra-low latency response times and low power modes necessary to support flagship smartphone features such as multiple high-resolution cameras, multiplayer gaming and AR/VR applications.”
Micron’s uMCP5 uses advanced 1y nm DRAM process technology and the world’s smallest 512Gb 96L 3D NAND die. The 297-ball grid array (BGA) package supports two-channel LPDDR5 with speeds up to 6,400 Mbps, a 50% performance increase over the previous-generation interface. The new package also provides the highest storage and memory density available for uMCP form factors in the market today, at 256 GB and 12 GB, respectively.
The uMCP is an ideal solution for Micron’s LPDDR5 DRAM. Micron’s next-generation LPDDR5 memory addresses the higher memory performance and lower energy consumption demands of 5G networks, which will start deploying globally at scale in 2020. Micron LPDDR5 allows 5G smartphones to process data at peak speeds of up to 6.4 Gbps, which is critical for preventing data-processing bottlenecks.
Micron’s uMCP5 package for LPDDR5 is available for immediate sampling to select partners.